An F-band 20.6Gbp/s QPSK transmitter in 65nm CMOS

Author

Bloch, Eli ; Socher, Eran

Author_Institution

Dept. of Electr. Eng., Technion - Israel Inst. of Technol., Haifa, Israel

fYear

2014

fDate

1-3 June 2014

Firstpage

299

Lastpage

302

Abstract

We hereby report the design and measurements of a 101-118 GHz 65 nm CMOS transmitter. The transmitter architecture is based on a two-step upconversion using a single 80 GHz LO with the quadrature phases generated by injection locked frequency dividers. Both BPSK and QPSK modulations with a maximum datarate of 20.6 Gbps are supported. A measured output power of -5 dBm at 115 GHz and an error-vector magnitude of 17.5% for 30 dB conversion-loss downconversion link are obtained. The chip core area is 0.21 mm² and a DC power consumption of 280 mW.

Keywords

CMOS integrated circuits; frequency dividers; millimetre wave integrated circuits; quadrature phase shift keying; radio transmitters; BPSK modulations; CMOS transmitter; F-band QPSK transmitter; bit rate 20.6 Gbit/s; conversion-loss downconversion link; error-vector magnitude; frequency 101 GHz to 118 GHz; frequency 80 GHz; injection locked frequency dividers; power 280 mW; size 65 nm; transmitter architecture; CMOS integrated circuits; Frequency measurement; Mixers; Phase shift keying; Radio frequency; Transmitters; CMOS integrated circuits; Injection-locked oscillators; Millimeter wave integrated circuits; Mixers; Phase modulation; Transmitters; Wireless Communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium, 2014 IEEE

Conference_Location

Tampa, FL

ISSN

1529-2517

Print_ISBN

978-1-4799-3862-9

Type

conf

DOI

10.1109/RFIC.2014.6851725

Filename

6851725