PreFPIX2: core architecture and results

Author

Hoff, J. ; Mekkaoui, A. ; Christian, D. ; Zimmerman, S. ; Cancelo, G. ; Yarema, R.

Author_Institution

Fermi Nat. Accel. Lab., Batavia, IL, USA

Volume

2

fYear

2000

fDate

2000

Abstract

FPIX is a pixel architecture designed for colliding-beam experiments at the Tevatron. Its most important application to date is the BTeV experiment. PreFPIX2 is a chip designed to test the FPIX core, i.e. the pixel control and readout architecture. This FPIX core will be mated to a periphery specific to a particular experiment. Earlier plans called for the BTeV FPIX chip to be designed in a rad-hard process. However, deep-submicron CMOS processes have demonstrated appropriate radiation tolerance at a lower cost and with greater reliability. Therefore, PreFPIX2 has been fabricated in a 0.25 micron process utilizing radiation tolerant design techniques. The architecture has undergone substantial development from earlier versions of FPIX. Most notable are the improvements to the column token passing scheme and to the end-of-column logic

Keywords

CMOS digital integrated circuits; digital readout; digital signal processing chips; high energy physics instrumentation computing; integrated circuit design; integrated circuit reliability; nuclear electronics; position sensitive particle detectors; transport protocols; 0.25 micron process; BTeV experiment; PreFPIX2 chip; colliding-beam experiments; column token passing scheme; core architecture; deep-submicron CMOS processes; design techniques; end-of-column logic; pixel architecture; pixel control; radiation tolerance; readout architecture; reliability; CMOS process; Clocks; Costs; Detectors; Hardware design languages; Logic; Monte Carlo methods; Radiation hardening; SPICE; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Nuclear Science Symposium Conference Record, 2000 IEEE

Conference_Location

Lyon

ISSN

1082-3654

Print_ISBN

0-7803-6503-8

Type

conf

DOI

10.1109/NSSMIC.2000.949879

Filename

949879