DocumentCode
1752344
Title
A novel dual-mode front-end stage for solid state detector applications
Author
Haralabidis, Nikos
Author_Institution
Inst. of Microelectron., NCSR Demokritos, Athens, Greece
Volume
2
fYear
2000
fDate
2000
Abstract
A novel front-end stage has been designed for use in solid state detector systems. Its novelty lies in the fact that it provides dual mode outputs: (i) a voltage step that corresponds to the total integrated charge and (ii) a fast differential signal that corresponds to the current pulse released by the detector. The first output signal is processed by a S-G shaper and is used for low/medium rate, low noise applications (peaking time 100 ns, ENC=100e-@2pF external capacitance). The second one is used for high rate applications (peaking time 25ns, ENC=350e-@2pF external capacitance). The circuit has been implemented in 0.6 μm CMOS process
Keywords
amplifiers; nuclear electronics; 2 pF; CMOS; S-G shaper; capacitance; front-end stage; low noise; peaking time; solid state detector; total integrated charge; Capacitance; Circuit topology; Detectors; Microelectronics; Multi-stage noise shaping; Resistors; Signal detection; Signal processing; Solid state circuits; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Nuclear Science Symposium Conference Record, 2000 IEEE
Conference_Location
Lyon
ISSN
1082-3654
Print_ISBN
0-7803-6503-8
Type
conf
DOI
10.1109/NSSMIC.2000.949900
Filename
949900
Link To Document