A multi-mode software-defined CMOS BPSK receiver SoC for the newly enhanced WWVB atomic clock broadcast

The first receiver system-on-chip (SoC) for the newly enhanced phase-modulation based WWVB broadcast is presented. Having an extensively digital architecture, and relying on the new features of the broadcast, it demonstrates 2-3 orders of receiver sensitivity superiority when compared to receiver ICs designed for the legacy WWVB broadcast. To allow for robust reception at very low signal levels, as well as in proximity to the station, it accommodates a dynamic range of over 130dB, representing the widest dynamic range found in any consumer-market receiver IC. The SoC is implemented in a 180nm CMOS process and has a die size of about 7mm².