A Nanoscale Memory Interface Scheme based on Hierarchical Memory Mapping

This paper presents a nanoscale to microscale interface for crossbar based memory architectures based on multi-stage memory mappers. By designing each stage carefully and by adding sufficient number of stages the total interface module size can be reduced to a size that is 3% to 5% the size of a one-stage mapper implemented in microscale. Thus most of the area advantage in using nanoscale memories can be retained. This architecture is also technology-independent and fault-tolerant. We have developed a model which relates the various design parameters to the size of the interface module and examined these design issues in depth.