On Practical Multiplexing Issues

Author

Beiu, Valeriu ; Sulieman, Mawahib H.

Author_Institution

College of Information Technology, United Arab Emirates University, Al Ain, United Arab Emirates, vbeiu@uaeu.ac.ae

Volume

1

fYear

2006

fDate

17-20 June 2006

Firstpage

310

Lastpage

313

Abstract

This paper investigates the behavior of multiplexing schemes in combination with elementary gates. The two schemes under investigation are MAJORITY- and NAND-multiplexing. The simulation results are for single-electron technology (SET), where the elementary components of the gates (capacitors in the case of capacitive-SET) are subjected to geometric variations. First, the elementary gates are compared in terms of their intrinsic probability of failure with respect to variations. Secondly, the two multiplexing schemes are weighted against the reliability enhancements they are able to bring into the system. This study gives insights into the behavior of fault-tolerant multiplexing schemes and shows how the logic styles, as well as the technology, could affect the overall reliability of a multiplexed system. Such aspects should be carefully weighted for the design of future nano-architectures.

Keywords

Fault-tolerance; multiplexing; reliability; single electron technology (SET); CMOS technology; Capacitors; Educational institutions; Electrons; Information technology; Nanoscale devices; Power dissipation; Redundancy; Solid modeling; Uncertainty; Fault-tolerance; multiplexing; reliability; single electron technology (SET);

fLanguage

English

Publisher

ieee

Conference_Titel

Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on

Print_ISBN

1-4244-0077-5

Type

conf

DOI

10.1109/NANO.2006.247637

Filename

1717087