Methods and Tools for Reliability Driven Defect-and Fault-tolerant Design of Nanosystems

In the recent past, CMOS manufacturing technology has been downscaled successfully to create feature sizes below 100 nm. But with the predicted demise of Moore’s law, continued success of the electronic industry will increasingly depend on emerging non-silicon nanotechnologies. CMOS or not, affordable manufacturing of defect-free nanosystems seems unlikely. Besides manufacturing defects, various transient faults will affect these systems. Therefore, there is a need for developing computing systems that are tolerant to defects and faults. Although several methodologies have been published in the literature to design defect-and fault-tolerant nanoscale systems, there is a severe lack of CAD tools to aid the design and analysis of such systems. In this paper, we develop multiple methodologies and tools to (i) design fault-tolerant nanosystems on architectures based on different nanotechnologies, and (ii) quantitatively analyze the performance of such nanosystems in terms of reliability, area and delay.