Optimizing and applying a scribe VC-TEG for the short-loop monitoring of Cu-via open failures

Cu-via open failures have become a major yield-loss factor for advanced SoCs. In this paper, we propose a new “scribe VC-TEG” for the short-loop monitoring of Cu-via open failures. The VC-TEG is to be embedded in the scribe lines of SoC product wafers. We introduce this TEG and discuss the optimization of its design. Critical area analysis (CAA) is utilized in quantitatively evaluating the TEG pattern configuration. We also demonstrate the merits of the TEG by introducing an example of its application on an actual mass production line.