Title :
Optimizing of process parameter and further step coverage improving regarding copper seed deposition for 50nm NAND flash
Author :
Pan, Ying-Chieh ; Chen, Chun-Chi ; Kuo, Hsien-Chang ; Chien, Hung-Ju
Author_Institution :
Powerchip Technol. Corp., Hsinchu, Taiwan
Abstract :
This paper proposed a very useful DOE trend in terms of Cu seed step coverage, necking CD, and side asymmetry improvement by optimizing of process parameters included bias of deposition, electromagnet, and bias of etch. And it displayed the best sidewall and bottom step coverage of 54% and 68% by a novel PVD sputtering source in which attributed from metal ion fraction increasing as applying in top CD 55nm and aspect ratio 3:1 of damascene structure. Besides void free in the ECP Cu gap filling is also obtained.
Keywords :
NAND circuits; coating techniques; copper; electromagnets; electronics industry; etching; metals; necking; sputtering; DOE; NAND flash; PVD sputtering source; copper seed deposition; electromagnet; etch; metal ion fraction; necking CD; process parameter optimization; Manufacturing; Radio frequency;
Conference_Titel :
Semiconductor Manufacturing (ISSM), 2010 International Symposium on
Conference_Location :
Tokyo
Print_ISBN :
978-1-4577-0392-8
Electronic_ISBN :
1523-553X
