DocumentCode
1753976
Title
Improvement of gate critical dimension for 40nm node device
Author
Yazawa, Hiroyuki ; Nishizawa, Atsushi ; Akimoto, Takeshi
Author_Institution
Renesas Electron. Corp., Yamagata, Japan
fYear
2010
fDate
18-20 Oct. 2010
Firstpage
1
Lastpage
3
Abstract
We tried to improve the variation of gate critical dimension(CD) within-wafer for 40nm node device at gate etching condition especially Bottom-Anti-Reflective-Coat (BARC) etching step. Gas diffusion influences in the etching chamber and temperature effects of electrostatic chucked (ESC) were investigated in this study. Finally it was achieved the optimal etching condition which significantly improved the within-wafer variation of the gate CD.
Keywords
antireflection coatings; etching; lithography; semiconductor device models; BARC etching; CD; ESC; bottom-antireflective-coat; electrostatic chuck; etching chamber; gas diffusion; gate critical dimension; gate etching condition; size 40 nm; temperature effect; Atmospheric measurements; Etching; Iterative closest point algorithm; Logic gates; Particle measurements; Shape;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing (ISSM), 2010 International Symposium on
Conference_Location
Tokyo
ISSN
1523-553X
Print_ISBN
978-1-4577-0392-8
Electronic_ISBN
1523-553X
Type
conf
Filename
5750245
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