Application of the SLID-ICV interconnection technology for the ATLAS pixel upgrade at SLHC

The presented R&D activity is focused on the development of a new detector for the upgrade of the ATLAS pixel system at SLHC at CERN, Geneva, employing thin pixel sensors together with a novel vertical integration technology. It consists of the Solid-Liquid-InterDiffusion (SLID) interconnection, which is an alternative to the standard solder bump-bonding, and Inter Chip Vias (ICV) for routing the signal vertically through the readout chips. The SLID interconnection is characterized by a very thin eutectic Cu-Sn alloy, achieved through the deposition of 5 μm of Cu on both sides, and 3 μm of Sn on one side only. The thin pixels are connected by the SLID process to the read out ASICs in the “chip to wafer” approach using tested known good dies. The inter chip vias are placed in the r/o chips before the SLID process in the “via last” approach. This approach gives the highest flexibility for the choice of the sensor and ASIC technology. The best possible sensors can be produced in a highly specialized technology on a dedicated process line and then in subsequent post-processing bonded to r/o ASICs coming from a standard CMOS line.