Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration

In this paper, two designs of a 3D interconnection architecture for stacked processor-memory large-scale integrations (LSIs) were investigated. With consideration given to stacking formation, a hierarchical 3D interconnection architecture with a tightly coupled processor-memory stacking configuration is proposed for achieving both higher throughput per unit area and lower power consumption in the vertical communications. Compared with a baseline stacking configuration, the proposed architecture has the 38% fewer vertical interconnects for the same throughput and reduces power consumption by 21%. The performances of three-dimensional stacking chips with 64-processor cores are also estimated. As a result, the proposed architecture achieves twenty-times-lower power consumption of inter-chip communications than conventional 2D integration. A uni-directional interconnect configuration and a 3D two-way flow-control protocol were also developed to achieve maximal utilization of the 3D interconnection network. According to simulations using a cycle-accurate stacking LSI model, the proposed technique achieves 90% utilization of the interconnection network, while a conventional design achieves less than 60%.