A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems

Author

Kim, Gil-Su ; Ikeuchi, Katsuyuki ; Daito, Mutsuo ; Takamiya, Makoto ; Sakurai, Takayasu

Author_Institution

Inst. of Ind. Sci., Univ. of Tokyo, Tokyo, Japan

fYear

2010

fDate

16-18 Nov. 2010

Firstpage

1

Lastpage

4

Abstract

A high-speed, low-power capacitive-coupling transceiver is presented for wireless wafer-level testing systems. The proposed transceiver achieves the highest data rate of 15Gb/s in 65nm CMOS process which is 7.5 times higher than previous work. The parallel termination increases the signal bandwidth in a printed circuit board (PCB) by 8.5 times. The glitch signaling reduces the static power consumption of conventional nonreturn-to-zero (NRZ) signaling by 30%. These two design techniques lead to the lowest energy per bit of 0.47pJ/b in a chip-to-board communication.

Keywords

CMOS integrated circuits; integrated circuit testing; low-power electronics; printed circuits; transceivers; CMOS process; bit rate 15 Gbit/s; capacitive-coupling transceiver; chip-to-board communication; design technique; glitch signaling; nonreturn-to-zero signaling; parallel termination; printed circuit board; size 65 nm; static power consumption; wireless wafer-level testing system; Bandwidth; Couplings; Integrated circuits; Optical signal processing; Testing; Transceivers; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

3D Systems Integration Conference (3DIC), 2010 IEEE International

Conference_Location

Munich

Print_ISBN

978-1-4577-0526-7

Type

conf

DOI

10.1109/3DIC.2010.5751456

Filename

5751456