3D system on chip memory interface based on modeled capacitive coupling interconnections

Author

Scandiuzzo, M. ; Cardu, R. ; Cani, S. ; Spolzino, S. ; Perugini, L. ; Franchi, E. ; Canegallo, R. ; Guerrieri, R.

Author_Institution

ARCES, Univ. of Bologna, Bologna, Italy

fYear

2010

fDate

16-18 Nov. 2010

Firstpage

1

Lastpage

4

Abstract

A memory interface for a 3D System-on-a-Chip based on capacitive coupling is implemented in 90nm CMOS technology. The design choices have been driven by an innovative 3D extraction and simulation flow. The presented work exploits AC capacitive coupling for chip-to-chip communication running up to 250MHz. The interface transfers 128 bit words between stacked SRAMs in an ARM-based System-on-a-Chip (SoC). The 3D memory interface achieves a total throughput of 32Gbit/sec with an average energy consumption of 35μW/Gbit/sec and an area occupancy of 0.05mm².

Keywords

CMOS integrated circuits; CMOS memory circuits; SRAM chips; integrated circuit design; integrated circuit interconnections; memory architecture; microprocessor chips; system-on-chip; 3D memory interface; 3D system on chip memory interface; 3D system-on-a-chip; AC capacitive coupling; ARM-based system-on-a-chip; CMOS technology; SoC; area occupancy; average energy consumption; chip-to-chip communication; design choices; innovative 3D extraction; modeled capacitive coupling interconnections; simulation flow; stacked SRAM; CMOS integrated circuits; Capacitance; Couplings; Electrodes; Integrated circuit interconnections; System-on-a-chip; Three dimensional displays;

fLanguage

English

Publisher

ieee

Conference_Titel

3D Systems Integration Conference (3DIC), 2010 IEEE International

Conference_Location

Munich

Print_ISBN

978-1-4577-0526-7

Type

conf

DOI

10.1109/3DIC.2010.5751459

Filename

5751459