• DocumentCode
    1754232
  • Title

    FEMU: A firmware-based emulation framework for SoC verification

  • Author

    Li, Hao ; Tong, Dong ; Huang, Kan ; Cheng, Xu

  • Author_Institution
    Microprocessor R&D Center, Peking Univ., Beijing, China
  • fYear
    2010
  • fDate
    24-29 Oct. 2010
  • Firstpage
    257
  • Lastpage
    266
  • Abstract
    Full-system emulation on FPGA(Field-Programmable Gate Array) with real-world workloads can enhance the confidence of SoC(System-on-Chip) design. However, since FPGA emulation requires complete implementation of key modules and provides weak visibility, it is time-consuming. This paper proposes FEMU, a hybrid firmware/hardware emulation framework for SoC verification. The core of FEMU is implemented by transplanting QEMU, a full-system emulator, from OS level to BIOS level, so we can directly emulate devices upon hardware. Moreover, FEMU provides programming interfaces to simplify device modeling in firmware. Based on an auxiliary set of hardware modules, FEMU allows hybrid full-system emulation with the combination of real hardware and emulated firmware model. Therefore, FEMU can facilitate full-system emulation in three aspects. First, FEMU enables full-system emulation with the minimum hardware implementation, so the DUT (Design Under Test) module can be verified under target application as early as possible. Second, by comparing the execution traces generated using real hardware and emulated firmware model, respectively, FEMU helps locate and fix bugs occurred in the full-system emulation. Third, by replacing un-verified hardware modules with emulated firmware models, FEMU helps isolating design issues in multiple modules. In a practical SoC project, FEMU helped us identify several design issues in full-system emulation. In addition, the evaluation results show that the emulation speed of FEMU is comparable with QEMU after transplantation.
  • Keywords
    field programmable gate arrays; firmware; formal verification; integrated circuit design; system-on-chip; BIOS level; FEMU; QEMU; SoC verification; design under test module; field-programmable gate array; firmware-based emulation framework; hybrid full-system emulation; system-on-chip design; Debugging; Emulation; Field programmable gate arrays; Hardware; Software; Synchronization; System-on-a-chip; Firmware; System Emulator; System-on-Chip; Verification;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2010 IEEE/ACM/IFIP International Conference on
  • Conference_Location
    Scottsdale, AZ
  • Print_ISBN
    978-1-6055-8905-3
  • Type

    conf

  • Filename
    5751510