Programmable fractional-ratio frequency multiplying clock generator

A new programmable delay-locked loop (DLL) based fractional frequency multiplying clock generator is presented. In contrast to conventional DLL-based clock generators that generate only integer clock multiplication, the proposed clock generator provides fractional-ratio frequency multiplication while maintaining the advantages of DLLs, such as the deskewing between the input and the output clocks. Implemented in a 0.13 μm 1.2 V CMOS process, the proposed clock generator achieves an effective peak-to-peak jitter of 7.5 ps and occupies an active area of 0.018 mm² while dissipating 9.0 mW at 1.5 GHz. The output frequency ranges from 0.85 to 1.5 GHz with programmable fractional multiplication ratios of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3.