A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications

Author

Saint-Laurent, Martin ; Bassett, Paul ; Lin, Kai-Chun ; Mohammad, Baker ; Yuhe Wang ; Xufeng Chen ; Alradaideh, Maen ; Wernimont, Tom ; Ayyar, Kartik ; Bui, Dan ; Galbi, Dwight ; Lester, Allan ; Pedrali-Noy, Marzio ; Anderson, Willie

Author_Institution

Qualcomm Technol., Inc., Austin, TX, USA

Volume

50

Issue

1

fYear

2015

fDate

Jan. 2015

Firstpage

81

Lastpage

91

Abstract

This paper describes the implementation of a Qualcomm Hexagon digital signal processor (DSP) in a 28 nm high-κ metal gate technology. The DSP is a multi-threaded very-long- instruction-word (VLIW) machine optimized for low leakage and energy efficiency. It uses a clock distribution network, clock gating cells, and pulsed latches that are optimized for low switching energy. The processor can be powered using a low-dropout (LDO) voltage regulator or a head switch. It operates from 255 MHz at 0.60 V to 1.24 GHz at 1.05 V. When operating from the LDO, the power consumption of the core can be as low as 58 μW/MHz, which is two to three times lower than comparable cores optimized for ultra-low voltage operation.

Keywords

clock distribution networks; digital signal processing chips; flip-flops; high-k dielectric thin films; multi-threading; voltage regulators; DSP; Qualcomm Hexagon digital signal processor; VLIW machine; clock distribution network; clock gating cells; energy-efficient mobile applications; frequency 255 MHz to 1.24 GHz; head switch; high-κ metal gate technology; high-performance mobile applications; low leakage; low switching energy; low-dropout voltage regulator; multithreaded very-long- instruction-word machine; on-chip LDO; power consumption; pulsed latches; size 28 nm; ultra-low voltage operation; voltage 0.60 V; voltage 1.05 V; Clocks; Delays; Digital signal processing; Latches; Logic gates; Switches; Capacitor-less LDO; DSP; clock power reduction; leakage optimization; low power design; near-threshold computing; power gating; pulsed latches;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2014.2371454

Filename

6983635