Title :
700 V ultra-low on-resistance DB-nLDMOS with optimised thermal budget and neck region
Author :
Kun Mao ; Ming Qiao ; Zhaoji Li ; Bo Zhang
Author_Institution :
State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
An ultra-low Ron,sp 700 V DB-nLDMOS (dual P-buried-layer nLDMOS) which uses 0.35 μm technology and full ion implantation technology is proposed. Experimental results show that with 800 V BVds, Ron,sp is only 10.7 Ω · mm2 which is the lowest value of triple RESURF (REduce SURface Field) LDMOS reported before. This mainly benefits from two aspects. First, thermal budgets of the process are strictly limited after implantation of the Pbury layer. Secondly, device sizes of the neck region are optimised to reduce Ron,sp which also suppress the JFET effect of the triple RESURF LDMOS.
Keywords :
MOS integrated circuits; MOSFET; ion implantation; junction gate field effect transistors; JFET effect; RESURF; dual P-buried-layer nLDMO; full ion implantation technology; neck region; reduce surface field; size 0.35 mum; thermal budget optimisation; ultra-ow on-resistance DB-nLDMOS; voltage 700 V; voltage 800 V;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2013.2287
