DocumentCode
1756040
Title
Switching Performance Optimization of a High Power High Frequency Three-Level Active Neutral Point Clamped Phase Leg
Author
Yang Jiao ; Sizhao Lu ; Lee, Fred C.
Author_Institution
Bradley Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ. Blacksburg, Blacksburg, VA, USA
Volume
29
Issue
7
fYear
2014
fDate
41821
Firstpage
3255
Lastpage
3266
Abstract
This paper introduces a three-level neutral point clamped (NPC) converter as a high power renewable energy grid interface. The phase leg building block is carefully designed to achieve high switching frequency and high efficiency. Different operating modes and switching loops in the phase leg are identified. Switching characteristics of each loop is evaluated by a double pulse test. Various parameters are taken into consideration as influential factors to loss and stress. An in-depth analysis of some special switching transients is also given. The test shows significant switching performance variance for different switching loops. Performance for each switch is optimized separately considering loss and stress tradeoff. A detailed loss model is built based on the test to calculate system loss distribution and loss breakdown under different switching modes and different operating conditions. The ANPC phase leg can be used to avoid undesirable switching loop and to reduce system loss under certain operating modes. The high-frequency NPC phase leg is tested under full power and the high efficiency design objective is verified.
Keywords
dielectric losses; power grids; renewable energy sources; switching convertors; ANPC phase leg; NPC; double pulse test; high power high frequency clamped phase leg; high power renewable energy grid interface; loss breakdown calculation; loss model; stress tradeoff; switching loops; switching modes; switching performance optimization; switching transients; system loss distribution calculation; three-level active neutral point clamped phase leg; three-level neutral point clamped converter; Inductance; Insulated gate bipolar transistors; Logic gates; Optical switches; Switching circuits; Switching frequency; Four-quadrant operating mode; neutral point clamp; parasitic inductance; switching loop; switching loss;
fLanguage
English
Journal_Title
Power Electronics, IEEE Transactions on
Publisher
ieee
ISSN
0885-8993
Type
jour
DOI
10.1109/TPEL.2013.2277657
Filename
6583314
Link To Document