NORA circuit design using neuron-MOS transistors

A No Race (NORA) dynamic logic using neuron-MOS transistor is presented. The circuit is designed using the n-channel neuron-MOS transistor instead of the nMOS logic block or pMOS logic block in the conventional NORA dynamic logic circuit. The proposed full-adder shows that the logic block of NORA circuit can be simplified by utilizing neuron-MOS transistor. A simple synthesis technique of the n-channel neuron-MOS logic block by employing summation signal is discussed. HSPICE simulation results using TSMC 0.35μm 2-ploy 4-metal CMOS process with 1.5V power supply, have verified the effectiveness of the proposed neuron-MOS-based NORA circuits. For comparison, the power consumption and the output delay of the proposed NORA adders are measured during the simulations.