• DocumentCode
    1757090
  • Title

    Assessment of Circuit Optimization Techniques Under NBTI

  • Author

    Xiaoming Chen ; Yu Wang ; Huazhong Yang ; Yuan Xie ; Yu Cao

  • Author_Institution
    Dept. of EE, Tsinghua Univ., Beijing, China
  • Volume
    30
  • Issue
    6
  • fYear
    2013
  • fDate
    Dec. 2013
  • Firstpage
    40
  • Lastpage
    49
  • Abstract
    This paper conducts a comprehensive study on existing circuit optimization techniques against NBTI, degradation mechanism that has become a critical reliability issue for nano-scaled IC design. These techniques are categorized by their intrinsic characteristics, and several important observations are made to give design guideline on NBTI mitigation.
  • Keywords
    circuit optimisation; integrated circuit design; integrated circuit reliability; negative bias temperature instability; NBTI mitigation; circuit optimization; degradation mechanism; nanoscaled IC design; reliability; Aging; Circuit optimization; Degradation; Delays; Equipment; Logic gates; Stress; Transistors; circuit optimization techniques; negative bias temperature instability; reliability;
  • fLanguage
    English
  • Journal_Title
    Design & Test, IEEE
  • Publisher
    ieee
  • ISSN
    2168-2356
  • Type

    jour

  • DOI
    10.1109/MDAT.2013.2266651
  • Filename
    6525391
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1757090