DocumentCode :
1757093
Title :
A Reconfigurable \\Delta \\Sigma ADC With Up to 100 MHz Bandwidth Using Flash Reference Shuffling
Author :
Caldwell, Thomas ; Alldred, David ; Zhao Li
Author_Institution :
Analog Devices Inc., Toronto, ON, Canada
Volume :
61
Issue :
8
fYear :
2014
fDate :
Aug. 2014
Firstpage :
2263
Lastpage :
2271
Abstract :
A reconfigurable 65-nm continuous-time low-pass delta-sigma modulator operates with a sampling frequency from 491 MHz to 1536 MHz, a signal bandwidth from 10 MHz to 100 MHz, and a dynamic range of 75.4 dB to 62.8 dB, respectively. Flash ADC calibration and reference shuffling with zipper rotation are used to improve the linearity of the flash, while also increasing the highest sampling rate and bandwidth of the modulator. Dynamic element matching using a randomized incremented pointer improves the linearity of the DAC.
Keywords :
analogue-digital conversion; calibration; bandwidth 10 MHz to 100 MHz; dynamic element matching; flash ADC calibration; flash reference shuffling; frequency 491 MHz to 1536 MHz; randomized incremented pointer; reconfigurable ΔΣ ADC; reconfigurable continuous-time low-pass delta-sigma modulator; size 65 nm; zipper rotation; Ash; Bandwidth; Clocks; Linearity; Modulation; Noise; Resistors; Analog-digital conversion; continuous-time systems; delta-sigma modulation;
fLanguage :
English
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-8328
Type :
jour
DOI :
10.1109/TCSI.2014.2333685
Filename :
6853391
Link To Document :
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