Fast Polar Decoders: Algorithm and Implementation

Author

Sarkis, Gabi ; Giard, Pascal ; Vardy, A. ; Thibeault, Claude ; Gross, Warren J.

Author_Institution

Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, QC, Canada

Volume

32

Issue

5

fYear

2014

fDate

41760

Firstpage

946

Lastpage

957

Abstract

Polar codes provably achieve the symmetric capacity of a memoryless channel while having an explicit construction. The adoption of polar codes however, has been hampered by the low throughput of their decoding algorithm. This work aims to increase the throughput of polar decoding hardware by an order of magnitude relative to successive-cancellation decoders and is more than 8 times faster than the current fastest polar decoder. We present an algorithm, architecture, and FPGA implementation of a flexible, gigabit-per-second polar decoder.

Keywords

block codes; decoding; error correction codes; field programmable gate arrays; linear codes; FPGA implementation; fast polar decoders; flexible polar decoder; gigabit-per-second polar decoder; polar codes; polar decoding hardware throughput; successive-cancellation decoders; symmetric memoryless channel capacity; Complexity theory; Maximum likelihood decoding; Parity check codes; Reliability; Systematics; Throughput; polar codes; storage systems; successive-cancellation decoding;

fLanguage

English

Journal_Title

Selected Areas in Communications, IEEE Journal on

Publisher

ieee

ISSN

0733-8716

Type

jour

DOI

10.1109/JSAC.2014.140514

Filename

6804939