Title :
Debug Automation for Logic Circuits Under Timing Variations
Author :
Dehbashi, Mehdi ; Fey, Gorschwin
Author_Institution :
Inst. of Comput. Sci., Univ. of Bremen, Bremen, Germany
Abstract :
This paper presents a novel approach to automate speedpath debugging taking into account variations. The proposed technique is based on Boolean Satisfiability. The approach is based on converting the timing behavior of a circuit into the functional domain, inserting a variation logic into the model, and using a Boolean Satisfiability solver to extract failing speedpaths.
Keywords :
computability; formal logic; logic circuits; program debugging; Boolean satisfiability; circuit timing behavior; debug automation; functional domain; logic circuits; speed-limiting paths; speedpath debugging; speedpath extraction; timing variations; variation logic; Aging; Debugging; Delays; Equipment; Integrated circuit modeling; Logic gates; Synchronization; automated debugging; failing speedpath; timing variation;
Journal_Title :
Design & Test, IEEE
DOI :
10.1109/MDAT.2013.2266393
