Title :
Device-Circuit Co-Optimization for Robust Design of FinFET-Based SRAMs
Author :
Gupta, Sumeet Kumar ; Roy, Kaushik
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
A set of device-circuit co-design techniques oriented to increase the resilience of FinFET SRAMs circuits is presented in this paper. Co-optimization of fin ratio, thickness, orientation and height are investigated and its impact on performance and area evaluated.
Keywords :
MOS memory circuits; SRAM chips; circuit optimisation; logic design; FinFET SRAM circuit; device circuit co-design technique; device circuit co-optimization; Aging; Circuit stability; Equipment; FinFETs; Logic gates; Optimization; Random access memory; Stability analysis; Co-design; FinFET; Process Variations; SRAM;
Journal_Title :
Design & Test, IEEE
DOI :
10.1109/MDAT.2013.2266394
