High-Frequency CMOS Active Inductor: Design Methodology and Noise Analysis

The potential of active inductors (AIs) has been often reduced by lack of accurate design methodologies and limitations due to the inherent noise sources. This paper deals with these two open issues for a high-frequency CMOS AI characterized by high-quality factor, low-power consumption, and low noise. First, it reports an effective design methodology for the implementation of high-frequency CMOS AIs with a high-quality factor. In particular, it shows how, through an advanced small-signal circuit model, to carry out an accurate and reliable design at high frequency (over 10 GHz) in modern nanoscale CMOS process. The design methodology is validated through cases of study at 13 GHz implemented in a standard 90-nm CMOS process and characterized experimentally. The results show that the AI exhibits an equivalent inductance close to 3.2 nH with an associated quality factor close to 200. After, it reports a noise analysis. It shows that the AI exhibits a very low level of noise, enabling its application to the implementation of high-quality factor low-noise LC tank in high-frequency building blocks of radio frequency front-ends. The results show that the AI exhibits a noise power spectral density lower than -150 dBm/Hz.