Title :
Efficient Process Shift Detection and Test Realignment
Author :
Yilmaz, Ender ; Ozev, Sule ; Butler, Kenneth M.
Author_Institution :
Freescale Semicond., Inc., Austin, TX, USA
Abstract :
Efficiency of test compaction is very important for production test time minimization. Poor test compaction methods either result in long test time or low test quality for analog and mixed-signal circuits. One of the most important factors in test compaction quality is accuracy of the representation of process statistics. Accurate representation is challenging since process characteristics are not stationary; thus, they need to be updated to maintain a reliable test quality level over the complete production run. Previous work in test compaction either does not take process shift into account or uses simplistic updating methods to avoid the cost of process relearning. In this paper, we propose an efficient relearning method that tracks changes in the process state of devices and generates a compact test list using relearned information for production test. The focus of this paper is production test of packaged devices. We model the mechanics of the process shift with a transformation function. We use information from a set of packaged devices of a reference (characterized) wafer to predict the characteristics of devices coming from other wafers using a very small number of learning samples. Fitting the transformation function enables us to map outdated process information to the up-to-date process information. We demonstrate the performance our method and compare it with previously published work using large scale production data of two distinct mixed-signal circuits. We show that our method maintains superior DPPM levels over large numbers of wafers and lots.
Keywords :
analogue circuits; integrated circuit testing; mixed analogue-digital integrated circuits; DPPM levels; analog circuits; mixed-signal circuits; process relearning cost; process shift detection; process statisticbrepresentation; production test time minimization; simplistic updating methods; test compaction methods; test quality level; test realignment; transformation function; up-to-date process information; Accuracy; Integrated circuits; Process design; Testing; Analog test; IC production test; process shift; test selection;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2013.2276614