Analysis and Suppression of Alias in Digitally Controlled Inverters

In digitally controlled inverters, the output voltage and current contain high-frequency harmonics due to the switching process. Unfortunately, the sampling frequency is often less than twice the bandwidth of measurement signal. Then, the aliasing phenomenon is brought into the sampling process and some low-frequency alias signals which cause power quality deterioration are produced. This paper presents a quantitative analysis to reveal the characteristic of the aliasing phenomenon in digitally controlled inverters. Specifically, the magnitude of alias signal will drop to zero and the phase will be inversed with some special sampling delays. Two alias suppression methods are then proposed by controlling the sampling delay. Steady-state error and low-frequency harmonics are significantly decreased with the proposed methods. The proposed methods have little delay so that the system has a better dynamic performance. The theoretical analysis and alias suppression strategies are validated by experimental results.