• DocumentCode
    175796
  • Title

    Establishing covert channel on shared cache architecture

  • Author

    Peili Yang ; Shien Ge ; Zhongqi Yang

  • Author_Institution
    Dept. of Electron. & Inf. Eng., Shazhou Polytech. Inst. of Technol., Suzhou, China
  • fYear
    2014
  • fDate
    19-21 Aug. 2014
  • Firstpage
    594
  • Lastpage
    599
  • Abstract
    Cache-based side channel attack has been extensively studied in recent years due to the possibly high damage it would cause. We are interested in replaying one instance of such attack to prove its feasibility and explore its details. Based on the literature review, we implemented a cache-based covert channel on a x86 machine and evaluated its performance by statistical analysis. Under certain limitations, we found that the channel can achieve a bandwidth as high as 1MB/s with over 99% accuracy, which is fairly enough to carry large amount of information.
  • Keywords
    cache storage; security of data; statistical analysis; cache-based side channel attack; covert channel; shared cache architecture; statistical analysis; x86 machine; Accuracy; Bandwidth; Encryption; Hardware; Interference; Microarchitecture; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Natural Computation (ICNC), 2014 10th International Conference on
  • Conference_Location
    Xiamen
  • Print_ISBN
    978-1-4799-5150-5
  • Type

    conf

  • DOI
    10.1109/ICNC.2014.6975902
  • Filename
    6975902