• DocumentCode
    1758052
  • Title

    Modeling On-Board Via Stubs and Traces in High-Speed Channels for Achieving Higher Data Bandwidth

  • Author

    Ki Jin Han ; Xiaoxiong Gu ; Kwark, Young H. ; Lei Shan ; Ritter, Mark B.

  • Author_Institution
    IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
  • Volume
    4
  • Issue
    2
  • fYear
    2014
  • fDate
    Feb. 2014
  • Firstpage
    268
  • Lastpage
    278
  • Abstract
    To achieve a target data bandwidth in high-speed channels, an on-board channel modeling study was presented in this paper. A design guideline was found by observing the variation of link performance, depending on parameters such as channel length, baud rate, and the number of signal layers. The channel performance was investigated using a newly developed parametric simulation environment supported by a fast multilayered via transition modeling tool. The extensive parameter sweep simulations showed that an allowable channel reach has a lower and an upper bound limited by stub via effect and trace loss, respectively. Under a specified channel reach, the aggregate data bandwidths were estimated using a particle swarm optimization routine, and a tradeoff relation among the wiring capability and the maximum allowable data rate was observed. From these observations, the approach provides a guideline to select the number of signal layers for achieving the required data bandwidth.
  • Keywords
    multichip modules; particle swarm optimisation; vias; aggregate data bandwidth; extensive parameter sweep simulation; fast multilayered via transition modeling tool; high speed channels; on-board channel modeling; on-board via stubs; parametric simulation; particle swarm optimization; stub via effect; trace loss; Bandwidth; Channel estimation; Channel models; Data models; Guidelines; Integrated circuit modeling; Manufacturing; Aggregate data bandwidth; Serializer/Deserializer (SerDes); backdrilling; baud rate; channel reach; design guideline; equalization; high-speed links; multilayered board; multiple package modules; parametric simulation; particle swarm optimization (PSO); transmission line loss; via stub effect;
  • fLanguage
    English
  • Journal_Title
    Components, Packaging and Manufacturing Technology, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    2156-3950
  • Type

    jour

  • DOI
    10.1109/TCPMT.2013.2277291
  • Filename
    6584771