DocumentCode :
1758122
Title :
A 100-kS/s 8.3-ENOB 1.7- 
Time-Domain Analog-to-Digital Converter
Author :
Younghoon Kim ; Changsik Yoo
Author_Institution :
Dept. of Electron. Eng., Integrated Circuits Lab., Hanyang Univ., Seoul, South Korea
Volume :
61
Issue :
6
fYear :
2014
fDate :
41791
Firstpage :
408
Lastpage :
412
Abstract :
A 100-kS/s time-domain analog-to-digital converter (TDADC) with successive approximation register architecture provides 8.3 effective bits. The time-domain comparator of the TDADC is realized with only one delay line consisting of a digitally controlled delay line and a voltage-controlled delay line. Therefore, the linearity degradation due to the mismatch between multiple delay lines can be avoided. The TDADC has been implemented in a 0.11-μm CMOS process with a 0.127-mm2 active silicon area. The TDADC consumes 1.7 μW from a 0.6-V supply voltage.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; comparators (circuits); delay lines; digital control; logic design; network analysis; silicon; time-varying networks; voltage control; CMOS process; ENOB; Si; TDADC; digitally controlled delay line; linearity degradation; power 1.7 muW; silicon area; size 0.11 mum; size 0.127 mm; successive approximation register architecture; supply voltage; time-domain analog-to-digital converter; time-domain comparator; voltage 0.6 V; voltage-controlled delay line; Capacitors; Delay lines; Delays; Solid state circuits; Temperature sensors; Time-domain analysis; Voltage control; Analog-to-digital converter (ADC); CMOS; delay line; successive approximation register (SAR); time-domain comparator;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2014.2319973
Filename :
6805213
Link To Document :
