Title :
On the Impact of Through-Silicon-Via-Induced Stress on 65-nm CMOS Devices
Author :
Weerasekera, Roshan ; Li, Hong Yu ; Yi, Lim Wei ; Sanming, Hu ; Shi, Jinglin ; Minkyu, Je ; Teo, Keng Hwa
Author_Institution :
Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore
Abstract :
Electrical evaluation of the impact of through-silicon via (TSV)-induced stress on 65-nm MOSFETs is presented in this letter. MOSFETs with varying widths and lengths were laid out at a minimum distance of 1.2 up to 16 μm from TSVs at different orientations. The TSV diameter, height, and dielectric barrier thickness are 8, 60, and 1 μm, respectively. Measured change of saturation current (Ion) of devices at the minimum distance is less than 4% for all the cases. The reliability of the devices was also investigated up to 1000 thermal cycles, between -55°C and 125 °C. No significant change in MOSFET performance is observed in comparison with the measurements before thermal cycling.
Keywords :
CMOS integrated circuits; MOSFET; integrated circuit reliability; three-dimensional integrated circuits; CMOS devices; MOSFET performance; TSV; electrical evaluation; saturation current; size 1 mum; size 65 nm; size 8 mum; thermal cycles; through-silicon-via-induced stress; Foundries; Logic gates; MOSFETs; Silicon; Stress; Through-silicon vias; Keep-out zone (KOZ); MOSFETs; three-dimensional integrated circuits (ICs); through-silicon via (TSV);
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2012.2228158
