DocumentCode
1758152
Title
Softcore Processor Optimization According to Real-Application Requirements
Author
Le Gal, Bertrand ; Jego, Christophe
Author_Institution
IMS Lab., Univ. of Bordeaux, Talence, France
Volume
5
Issue
1
fYear
2013
fDate
41334
Firstpage
4
Lastpage
7
Abstract
Nowadays, embedded processor cores are integrated into most system-on-chip (SoC). Processor cores can be designed to be dedicated for an SoC. However, reusing of generic processors is often preferred due to time to market constraint. Such processors have drawbacks in terms of hardware complexity and power consumption. Indeed, some of their instructions and hardware resources are useless. These area and energy inefficiencies are problematic for low-cost and low-energy systems. In this paper, we propose a methodology for automatically reducing processor functionalities and the resulting hardware complexity according to real-application requirements. This approach was evaluated on two open-source processor cores. The results show that the average area and power consumption savings are over 20% on both application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) technologies.
Keywords
field programmable gate arrays; system-on-chip; ASIC; FPGA; SoC; application-specific integrated circuit; area inefficiencies; embedded processor cores; energy inefficiencies; field-programmable gate array technologies; generic processors; hardware complexity; hardware resources; low-cost systems; low-energy systems; power consumption; real-application requirements; softcore processor optimization; system-on-chip; time to market constraint; Application specific integrated circuits; Benchmark testing; Computer architecture; Field programmable gate arrays; Hardware; Plasmas; Power demand; Embedded softcore processor; instruction set architecture (ISA); methodology;
fLanguage
English
Journal_Title
Embedded Systems Letters, IEEE
Publisher
ieee
ISSN
1943-0663
Type
jour
DOI
10.1109/LES.2012.2234080
Filename
6381445
Link To Document