A Method for Reducing Noise and Complexity in Yield Analysis for Manufacturing Process Workflows

In this paper, we present an approach to analyze a process workflow for the fabrication of semiconductor integrated circuits in order to identify the source(s) of yield loss. Specifically, we address computational challenges using Bayesian analysis to isolate key process steps affecting the global yield loss of a given workflow. Bayesian inference algorithms incur a heavy computational penalty when applied to large graphs with repetitions, un-modeled interactions, and reentrants, all of which are commonly found in semiconductor manufacturing workflows. We are able to improve the performance of the diagnostic inference process by “folding” and “clustering” nodes, where possible, to simplify the analysis. We also include the effect of un-modeled interactions called latent effects by using a memory efficient auxiliary relaxation. Finally, we present a method to strategically reverse the simplifications, when necessary, so that the accuracy of the inference result is not compromised. The analysis process is shown to be effective at identifying the root cause of global yield discrepancies in a semiconductor manufacturing workflow. We also show that auxiliary relaxation improves the convergence properties of the inference algorithm and reduces the net uncertainty and noise in the final result.