System-Level Design Framework for Insertion-Loss-Minimized Optical Network-on-Chip Router Architectures

An optical network-on-chip (NoC) has attracted increasing attention with the advancement of silicon photonics technology due to the explosive growth in communication traffic in system-on-chip and the diminishing returns of miniaturized metal interconnect. Compared with the traditional metallic interconnect, the optical interconnect has superior effective bandwidth, transmission latency, and power consumption. In this paper, we establish an algorithmic optical router design framework to minimize the insertion loss, which is the loss of signal power resulting from the insertion of microring resonators and waveguide crossings. By incorporating system-level considerations on the topology, routing algorithm, and traffic pattern in the optical NoC, the proposed technique provides a rapid design environment for a wide range of application-specific optical NoC architectures with minimized optical signal power loss.