DocumentCode :
1759410
Title :
Barrier Properties of CVD Mn Oxide Layer to Cu Diffusion for 3-D TSV
Author :
Kang-Wook Lee ; Hao Wang ; Ji-Cheol Bea ; Murugesan, Mariappan ; Sutou, Y. ; Fukushima, Tetsuya ; Tanaka, T. ; Koike, Junichi ; Koyanagi, Mitsumasa
Author_Institution :
New Ind. Creation Hatchery Center, Tohoku Univ., Sendai, Japan
Volume :
35
Issue :
1
fYear :
2014
fDate :
Jan. 2014
Firstpage :
114
Lastpage :
116
Abstract :
The effect of CVD Mn oxide layer as a barrier layer to Cu diffusion for 3-D TSV was characterized. The impact of oxide substrate on the barrier property of a planar Mn oxide was evaluated by XPS method. Planar Mn oxide layer of 20-nm thickness formed over thermal oxide showed an excellent barrier property to Cu diffusion after annealing at 500°C, whereas the Mn oxide over P-TEOS oxide was good enough up to 400°C annealing. On the other hand, the barrier property of Mn oxide upon O3-TEOS oxide was not as good as thermal and P-TEOS oxides. The effect of a vertical Mn oxide layer as a barrier layer to Cu diffusion from Cu TSV was evaluated by C-t analysis. Vertical Mn oxide layer with 20-nm thickness formed on P-TEOS oxide liner in TSV showed better barrier property, when compared with the sputtered Ta barrier layer, up to 400°C annealing condition. However, the barrier property of CVD Mn oxide layer was degraded after annealing at 500°C.
Keywords :
X-ray photoelectron spectra; annealing; chemical vapour deposition; copper; manganese; three-dimensional integrated circuits; 3D TSV; CVD manganese oxide layer; Cu; Mn; O3-TEOS oxide; P-TEOS oxide liner; XPS method; annealing condition; barrier property; size 20 nm; temperature 500 degC; thermal oxide; Annealing; Atomic layer deposition; Manganese; Silicon; Substrates; Through-silicon vias; CVD Mn oxide; Cu TSV; Cu diffusion; barrier layer; capacitance-time (C-t);
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/LED.2013.2287879
Filename :
6665012
Link To Document :
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