High-efficiency CMOS stacked-FET power amplifier for W-CDMA applications using SOI technology

Author

Jeon, M.-S. ; Woo, Jiyong ; Kim, Unha ; Kwon, Youngwoo

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea

Volume

49

Issue

8

fYear

2013

fDate

April 11 2013

Firstpage

564

Lastpage

566

Abstract

A linear CMOS power amplifier (PA) is developed for wideband code-division multiple-access (W-CDMA) application using 0.18 μm silicon-on-insulator (SOI) technology. By adopting a quadruple-stacked FET structure, 1W of output power is achieved at 4V supply voltage. A negative capacitance circuit is employed to maximise the efficiency of the PA by cancelling out the excessive capacitance at the source terminal of the common-gate stage. Besides, a lineariser based on the variable capacitor circuit is added to reduce the inherent AM-PM distortion of the CMOS FET. Using W-CDMA modulation at 837MHz, the fabricated PA module delivers a PAE of 47.5% and an adjacent channel leakage ratio of - 36dBc at the output power of 27.1dBm.

Keywords

CMOS analogue integrated circuits; MOSFET; capacitance; capacitors; code division multiple access; power amplifiers; silicon-on-insulator; wideband amplifiers; AM-PM distortion; CMOS FET; PAE; SOI technology; W-CDMA application; W-CDMA modulation; channel leakage ratio; excessive capacitance; fabricated PA module; frequency 837 MHz; high-efficiency CMOS stacked-FET power amplifier; linear CMOS power amplifier; lineariser; negative capacitance circuit; power 1 W; quadruple-stacked FET structure; silicon-on-insulator technology; size 0.18 mum; source terminal; variable capacitor circuit; voltage 4 V; wideband code-division multiple-access apllication;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el.2012.3627

Filename

6527562