Partially Depleted SOI Versus Deep N-Well Protected Bulk-Si MOSFETs: A High-Temperature RF Study for Low-Voltage Low-Power Applications

The design options for low-voltage low-power (LVLP) applications are not limited to the circuit level, but it should start with the right choice of device technology and architecture. This paper presents a comparative study between a special structure of bulk MOSFET called the deep n-well protected device and the partially depleted silicon-on-insulator device. This paper shows the advantage of each device for different operation schemes while concentrating on the RF behavior for very low bias conditions. The study shows the lower limit for the bias conditions for the devices to correctly operate in RF. It also presents the effect of high temperature on the key figures of merit for dc and RF operations for high-performance and LVLP operation regimes.