DocumentCode
1760274
Title
Evaluating Overheads of Multibit Soft-Error Protection in the Processor Core
Author
Szafaryn, L.G. ; Meyer, Brett H. ; Skadron, Kevin
Author_Institution
Univ. of Virginia, Charlottesville, VA, USA
Volume
33
Issue
4
fYear
2013
fDate
July-Aug. 2013
Firstpage
56
Lastpage
65
Abstract
The Svalinn framework provides comprehensive analysis of multibit error protection overheads to facilitate better architecture-level design choices. supported protection techniques include hardening, parity, error-correcting code, parity prediction, residue codes, and spatial and temporal redundancy. The overheads of these are characterized via synthesis and, as a case study, presented here in the context of a simple openrisc core.
Keywords
error correction codes; microprocessor chips; radiation hardening (electronics); redundancy; residue codes; Svalinn framework; error-correcting code; hardening code; multibit error protection overheads; multibit soft-error protection; openrisc core; parity code; parity prediction; processor core; residue codes; spatial redundancy; temporal redundancy; Error correction codes; Logic circuits; Multicore processing; Random access memory; Redundancy; Svalinn; architecture; multibit error protection; reliability;
fLanguage
English
Journal_Title
Micro, IEEE
Publisher
ieee
ISSN
0272-1732
Type
jour
DOI
10.1109/MM.2013.68
Filename
6527889
Link To Document