Use of Commercial FPGA-Based Evaluation Boards for Single-Event Testing of DDR2 and DDR3 SDRAMs

The speed, tight timing requirements packaging and complicated error behavior of DDR2 and DDR3 SDRAMs pose significant challenges for single-event testing. Often, each new generation will require an expensive new tester with a state-of-the-art controller for the memory. We explore the trade-offs in the use of commercial FPGA based evaluation boards for radiation testing DDR2 and DDR3 SDRAMs. We evaluate the resulting data quality and discuss tester performance while also elucidating and comparing SEE susceptibilities in DDR2 and DDR3 SDRAMs.