Experimental Soft Error Rate of Several Flip-Flop Designs Representative of Production Chip in 32 nm CMOS Technology

Author

Gasiot, Gilles ; Glorieux, M. ; Clerc, Sylvain ; Soussan, Dimitri ; Abouzeid, Fady ; Roche, Philippe

Author_Institution

Central CAD & DS, ST Microelectron., Crolles, France

Volume

60

Issue

6

fYear

2013

fDate

Dec. 2013

Firstpage

4226

Lastpage

4231

Abstract

This paper shows alpha experimental Soft Error Rate characterization of several standard and hardened Flip-Flop architectures processed in a 32 nm technology. It showsthe effecton the alpha Soft Error Rateof experimental parameters such as algorithm (static vs.kdynamic), data filling the register, etc. 12 data patterns onmore than 5Flip-Floptypes(including DICE-like design)are reported in this articlein order to help the radiation engineer to choose the best algorithm/pattern for its SER characterizations.

Keywords

CMOS logic circuits; flip-flops; radiation hardening (electronics); CMOS technology; DICE-like design; SER characterization; alpha experimental soft error rate characterization; alpha soft error rate; data filling; data patterns; flip-flop design; hardened flip-flop architecture; production chip; radiation engineer; size 32 nm; standard flip-flop architecture; Clocks; Error analysis; Flip-flops; Integrated circuit modeling; Shift registers; Alpha experiments; Flip-Flop; shift register; soft error rate;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2013.2284546

Filename

6665184