DocumentCode :
1760678
Title :
Coming Challenges with Terabit-per-Second Data Communication
Author :
Zabinski, P. ; Gilbert, Barry ; Daniel, E.
Author_Institution :
Special Purpose Processor Dev. Group, Mayo Clinic, Rochester, MN, USA
Volume :
13
Issue :
3
fYear :
2013
fDate :
thirdquarter 2013
Firstpage :
10
Lastpage :
20
Abstract :
The growth in network data-rates is outpacing several constituent technologies, which is creating new challenges that cannot be readily overcome through simple extensions of previous approaches. This paper contributes by identifying new challenges facing the emerging data-communication protocols in the 400 Gb/s to 1 Tb/s range. Three particular challenges are presented along with their respective design implications and options: off-chip data interfaces; on-chip data busses; and off-chip buffering.
Keywords :
data communication; electronic data interchange; protocols; bit rate 40 Gbit/s to 1 Tbit/s; off-chip buffering; off-chip data interface; on-chip data bus; terabit-per-second data communication protocol network; Complexity theory; Data processsing; High-speed optical techniques; Optical buffering; Optical fiber networks;
fLanguage :
English
Journal_Title :
Circuits and Systems Magazine, IEEE
Publisher :
ieee
ISSN :
1531-636X
Type :
jour
DOI :
10.1109/MCAS.2013.2271441
Filename :
6585766
Link To Document :
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