DocumentCode

1760693

Title

Performance and Reliability of ${\\rm Gd}_{2}{\\rm O}_{3}$ and Stacked ${\\rm Gd}_{2}{\\rm O}_{3}\\hbox {-}</h1></div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Author</span></div><div class='col-12 col-md-9 leftDirection leftAlign'><h2 class='mb-0 fw-semibold'>Padmanabhan, Regina ; Bhat, Nagaraj ; Mohan, Swati</h2></div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Author_Institution</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Volume</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>60</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Issue</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>5</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>fYear</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>2013</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>fDate</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>41395</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Firstpage</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>1523</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Lastpage</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>1528</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Abstract</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>Gd<sub>2</sub>O<sub>3</sub>-based metal-insulator-metal capacitors have been characterized with single layer (Gd<sub>2</sub>O<sub>3</sub>) and bilayer (Gd<sub>2</sub>O<sub>3</sub>/Eu<sub>2</sub>O<sub>3</sub> and Eu<sub>2</sub>O<sub>3</sub>/Gd<sub>2</sub>O<sub>3</sub>) stacks for analog and DRAM applications. Although single layer Gd<sub>2</sub>O<sub>3</sub> capacitors provide highest capacitance density (15 fF/μm<sup>2</sup>), they suffer from high leakage current density, poor capacitance density-voltage linearity, and reliability. The stacked dielectrics help to reduce leakage current density (1.2×10<sup>-5</sup> A/cm<sup>2</sup> and 2.7 × 10<sup>-5</sup> A/cm<sup>2</sup> for Gd<sub>2</sub>O<sub>3</sub>/Eu<sub>2</sub>O<sub>3</sub> and Eu<sub>2</sub>O<sub>3</sub>/Gd<sub>2</sub>O<sub>3</sub>, respectively, at -1 V), improve quadratic voltage coefficient of capacitance (331 ppm/V<sup>2</sup> and 374 ppm/V<sup>2</sup> for Gd<sub>2</sub>O<sub>3</sub>/Eu<sub>2</sub>O<sub>3</sub> and Eu<sub>2</sub>O<sub>3</sub>/Gd<sub>2</sub>O<sub>3</sub>, respectively, at 1 MHz), and improve reliability, with a marginal reduction in capacitance density. This is attributed to lower trap heights as determined from Poole-Frenkel conduction mechanism, and lower defect density as determined from electrode polarization model.</div></div> </li> <li class='list-group-item border-0 py-3 px-0'> <div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Keywords</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>DRAM chips; MIM devices; capacitance; capacitors; current density; europium compounds; gadolinium compounds; semiconductor device reliability; DRAM applications; Gd2O3-based metal-insulator-metal capacitors; Gd<sub>2</sub>O<sub>3</sub>-Eu<sub>2</sub>O<sub>3</sub>; Poole-Frenkel conduction mechanism; analog applications; bilayer stacks; capacitance density-voltage linearity; defect density; electrode polarization model; frequency 1 MHz; leakage current density; single layer stacks; stacked dielectrics; trap heights; Capacitance; Capacitors; Leakage current; MIM capacitors; Reliability; Stress; <formula formulatype=$ ${rm Eu}_{2}{rm O}_{3}$; ${rm Gd}_{2}{rm O}_{3}$; constant current stress (CCS); constant voltage stress (CVS); metal-insulator-metal (MIM); reliability; voltage coefficient of capacitance (VCC);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2013.2249854

Filename

6481433

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1760693