Title :
MOST Moderate–Weak-Inversion Region as the Optimum Design Zone for CMOS 2.4-GHz CS-LNAs
Author :
Fiorelli, Riccardo ; Silveira, F. ; Peralias, E.
Author_Institution :
Inst. de Microelectron. de Sevilla (IMSE-CNM), Consejo Super. de Investig. Cientificas & Univ. de Sevilla, Sevilla, Spain
Abstract :
In this paper, the MOS transistor (MOST) moderate-inversion (MI)-weak-inversion (WI) region is shown to be the optimum design zone for CMOS 2.4-GHz common-source low-noise amplifiers (CS-LNAs) focused on low power consumption applications. This statement is supported by a systematic study where the MOST is analyzed in all-inversion regions using an exhaustive CS-LNA noise-figure (NF)-power-consumption optimization technique with power gain constraint. Effects of bias choke resistance and MOST capacitances are carefully included in the study to obtain more accurate results, especially for the MI-WI region. NF, power consumption, and gain versus the inversion region are described with design space maps, providing the designer with a deep insight of their tradeoffs. The Pareto-optimal design frontier obtained by calculation-showing the MI-WI region as the optimum design zone-is reverified by extensive electrical simulations of a high number of designs. Finally, one 90-nm 2.4-GHz CS-LNA Pareto optimal design is implemented. It achieves the best figure of merit considering under-milliwatt CS-LNAs published designs, consuming 684 μW, an NF of 4.36 dB, a power gain of 9.7 dB, and a third-order intermodulation intercept point of -4 dBm with load and source resistances of 50 Ω.
Keywords :
CMOS analogue integrated circuits; MOSFET; Pareto optimisation; UHF amplifiers; UHF integrated circuits; integrated circuit design; low noise amplifiers; low-power electronics; CMOS common-source low-noise amplifiers; MOS transistor; Pareto-optimal design frontier; all-inversion regions; bias choke resistance; capacitances; design space maps; exhaustive CS-LNA noise-figure-power-consumption optimization technique; frequency 2.4 GHz; gain 9.7 dB; load resistance; low power consumption applications; moderate-weak-inversion region; noise figure 4.36 dB; optimum design zone; power 684 muW; power gain constraint; resistance 50 ohm; size 90 nm; source resistance; third-order intermodulation intercept point; Gain; Impedance; Inductors; Noise; Noise measurement; Optimization; Table lookup; $g_m/I_D$; Common-source low-noise amplifiers (CS-LNAs); Pareto optimal; design methodology; low power; moderate inversion (MI); optimization; weak-inversion (WI) noise figure (NF);
Journal_Title :
Microwave Theory and Techniques, IEEE Transactions on
DOI :
10.1109/TMTT.2014.2303476