A Compact Model for Erratic Event Simulation in Flash Memory Arrays

The simulation of the erratic bits phenomenon in Flash memory arrays for reliability projections has been a matter of study in the last decade from many standpoints. However, the majority of the developed simulation framework lacked both a direct link with the physics underlying the phenomenon and an easy integration with circuit simulators for fast analysis. In this paper, we have developed a compact model for erratic events starting from the PSP-model description of a Flash cell using Verilog-A. The model has been focused on the reproduction of the overerase phenomenon in a 90-nm NOR Flash array. Its accurate and fast simulation capabilities allowed the evaluation of the array reliability against the erratic erase operation.