Title :
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking
Author :
Fluhr, Eric J. ; Baumgartner, Steve ; Boerstler, David ; Bulzacchelli, John F. ; Diemoz, Timothy ; Dreps, Daniel ; English, George ; Friedrich, J. ; Gattiker, Anne ; Gloekler, Tilman ; Gonzalez, Christopher ; Hibbeler, Jason D. ; Jenkins, Keith A. ; Yong
Author_Institution :
STG, IBM, Austin, TX, USA
Abstract :
POWER8™ is a 12-core processor fabricated in IBM´s 22 nm SOI technology with core and cache improvements driven by big data applications, providing 2.5× socket performance over POWER7+™. Core throughput is supported by 7.6 Tb/s of off-chip I/O bandwidth which is provided by three primary interfaces, including two new variants of Elastic Interface as well as embedded PCI Gen-3. Power efficiency is improved with several techniques. An on-chip controller based on an embedded PowerPC™ 405 processor applies per-core DVFS by adjusting DPLLs and fully integrated voltage regulators. Each voltage regulator is a highly distributed system of digitally controlled microregulators, which achieves a peak power efficiency of 90.5%. A wide frequency range resonant clock design is used in 13 clock meshes and demonstrates a minimum power savings of 4%. Power and delay efficiency is achieved through the use of pulsed-clock latches, which require statistical validation to ensure robust yield.
Keywords :
digital control; digital phase locked loops; microprocessor chips; multiprocessing systems; scaling circuits; silicon-on-insulator; voltage regulators; DPLL; DVFS; IBM; IO bandwidth; PCI Gen-3; POWER7+; POWER8 processor; PowerPC 405 processor; SOI technology; big data application; cache improvement; clock mesh; core throughput; delay efficiency; digital phase locked loop; digitally controlled microregulator; dynamic voltage and frequency scaling; efficiency 90.5 percent; elastic interface; integrated voltage regulation; on-chip controller; power efficiency; power saving; pulsed-clock latch; resonant clocking; silicon on insulator technology; size 22 nm; socket performance; voltage regulator; wide frequency range resonant clock design; Bandwidth; Clocks; Latches; Logic gates; Receivers; Regulators; Voltage control; Clocking; elastic interface; microprocessor; power efficiency; power management; pulsed latch; serdes; voltage regulator;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2014.2358553