Low-Pass Delta-Delta-Sigma ADC

The intrinsic low dynamic range of a DC SQUID (<; one flux quantum) usually prohibits its use as a quantizer in a high dynamic range ADC. Here we show a new ADC architecture that incorporates the DC SQUID as a quantizer while enabling dynamic range extension using digital feedback. Using the SQUID as a quantizer, we are able to construct a low pass delta-delta-sigma ADC. To accommodate bipolar signals, a carrier is injected to make the SQUID output voltage at the center of its linear range. The subtraction of carrier before applying digital feedback dominates the latency of the feedback loop measured in clock period. Low feedback latency facilitates higher integrator gain while satisfying the stability criterion, leading to higher LSB, and higher dynamic range. At higher clock frequencies, the increased feedback loop latency necessitates reducing LSB and hence reduced dynamic range. Hence the performance of such ADC does not necessarily scale with increased clock frequency. Here we present performance analysis of such ADC including functional simulation, circuit simulation, and experimental test results.