DocumentCode :
1762739
Title :
A High-Performance On-Chip Bus (MSBUS) Design and Verification
Author :
Xiaokun Yang ; Andrian, Jean H.
Author_Institution :
Adv. Micro Devices Inc., Beijing, China
Volume :
23
Issue :
7
fYear :
2015
fDate :
42186
Firstpage :
1350
Lastpage :
1354
Abstract :
This brief proposes a high-performance system-on-chip bus protocol termed the master-slave bus (MSBUS). Considering the inevitable tradeoff among area, throughput and energy efficiency, the control bus is developed as a low-cost and low-power bus, and the data bus is created as a high-throughput full-duplex bus with the feature of block data transfer. To evaluate the bus performance, we create four analytical models including transfer time consumption (TC), wire efficiency (WE), valid data bandwidth (VDB) and dynamic energy efficiency. Then, the advanced high-performance bus-, advanced eXensible interface (AXI)-, and MSBUS-based direct memory access (DMA) are developed as a case study of hardware implementation. It is observed that MSBUS DMA costs less hardware resources and achieves higher performance, especially in the block transfer mode. For instance, the results from both the analytical models and the practical tests show that the TC of MSBUS is close to 63% of the AXI, the WE and VDB of MSBUS are almost 2.3 and 1.6 times of the AXI respectively, and the energy consumption is half of AXI in the block transfer mode.
Keywords :
integrated circuit design; protocols; system buses; system-on-chip; AXI-based DMA; MSBUS-based direct memory access; advanced eXensible interface-based DMA; advanced high-performance bus-based DMA; block data transfer feature; block transfer mode; control bus; data bus; dynamic energy efficiency; energy consumption; energy efficiency; hardware implementation; high-performance MSBUS verification; high-performance on-chip bus design; high-performance system-on-chip bus protocol; high-throughput full-duplex bus; low-power bus; master-slave bus; transfer time consumption; valid data bandwidth; wire efficiency; Analytical models; Hardware; Measurement; Protocols; System-on-chip; Very large scale integration; Wires; Dynamic energy efficiency; system-on-chip (SoC); valid data bandwidth (VDB); wire efficiency (WE); wire efficiency (WE).;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2014.2334351
Filename :
6857438
Link To Document :
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