Impact of Extrinsic Capacitances on FinFET RF Performance

Author

Tinoco, J.C. ; Salas Rodriguez, Silvestre ; Martinez-Lopez, A.G. ; Alvarado, J. ; Raskin, J.

Author_Institution

Telecommun. Dept. of the Eng. Sch., Nat. Autonomous Univ. of Mexico, Mexico City, Mexico

Volume

61

Issue

2

fYear

2013

fDate

Feb. 2013

Firstpage

833

Lastpage

840

Abstract

Triple-Gate FinFETs have been demonstrated to be promising to push further the down scaling of CMOS technology, because of their high immunity against the so-called short channel effects. However, due to their three-dimensional (3-D) architecture, strong degradation of their analog characteristics has been reported, basically due to large extrinsic resistances and capacitances. In this paper, based on measurements and 3-D numerical simulations, we analyze the impact of the extrinsic gate capacitances on the RF behavior of FinFETs. It is shown that the reduction of the fin spacing, the modification of the fin geometrical aspect ratio (height/width) as well as the optimization of the fin spacing-fin Source/Drain extension ratio can significantly improve the FinFET RF performance.

Keywords

CMOS integrated circuits; MOSFET; numerical analysis; optimisation; 3D architecture; 3D numerical simulations; CMOS technology; FinFET RF performance; extrinsic capacitances; optimization; short channel effects; source/drain extension ratio; three-dimensional architecture; Capacitance; Electrodes; FinFETs; Logic gates; Radio frequency; Transmission line matrix methods; 3-D numerical simulations; Cut-off frequency; FinFETs; RF characterization; extrinsic capacitances;

fLanguage

English

Journal_Title

Microwave Theory and Techniques, IEEE Transactions on

Publisher

ieee

ISSN

0018-9480

Type

jour

DOI

10.1109/TMTT.2012.2231697

Filename

6387636