• DocumentCode
    1764311
  • Title

    Performance Enhancement on an InGaP/InGaAs PHEMT With an Electrophoretic Deposition Gate Structure

  • Author

    Chun-Chia Chen ; Huey-Ing Chen ; Po-Cheng Chou ; Jian-Kai Liou ; Yung-Jen Chiou ; Jung-Hui Tsai ; Wen-Chau Liu

  • Author_Institution
    Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan
  • Volume
    35
  • Issue
    1
  • fYear
    2014
  • fDate
    Jan. 2014
  • Firstpage
    18
  • Lastpage
    20
  • Abstract
    Interesting pseudomorphic high electron mobility transistors using an electrophoretic deposition (EPD) approach are fabricated and studied. Due to the low-temperature deposited gate structure, the studied device exhibits enhanced performance with less thermal damages and improved Schottky contact properties by EPD approach. In comparison with a thermal evaporation (TE) device, the higher turn-on voltage, lower gate current, and lower interface state density are observed for the EPD device. For the gate dimension of 1 × 100 μm2 the EPD device shows the higher maximum drain saturation current of 242.2 (231.9) mA/mm and excellent maximum extrinsic transconductance of 151.6 (132.5) mS/mm at 300 (420) K. Besides, the EPD device presents a comparable RF performance as compared with the TE one. Due to the improved device performance and advantages of low cost, simple process, flexible deposition on varied substrate, and adjustable metal grain size, the reported EPD approach shows the promise for high-performance device applications.
  • Keywords
    III-V semiconductors; Schottky barriers; electrodeposition; electrophoresis; gallium arsenide; gallium compounds; grain size; high electron mobility transistors; indium compounds; interface states; InGaP-InGaAs; InGaP/InGaAs PHEMT; RF performance; Schottky contact properties; electrophoretic deposition; electrophoretic deposition gate structure; maximum drain saturation current; metal grain size; performance enhancement; pseudomorphic high electron mobility transistors; temperature 300 K; thermal damages; Gallium arsenide; Logic gates; Metals; PHEMTs; Performance evaluation; Schottky barriers; Substrates; EPD; Fermi-level pinning effect; PHEMT; reverse micelle;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2013.2288108
  • Filename
    6670683